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Description: 写CRC编解码程序时,整理的文件,压缩文件既有理论说明,也有源代码。源代码格式用C,VHDL,Verilog。-write CRC codec procedures, collating documents, compressed files both theoretical statements, and the active code. Source code format C, VHDL, Verilog.
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Size: 706776 |
Author: cdl |
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Description: 循环冗余校验,crc_16,主要运用在数字通信系统。用verilog HDL编写
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Size: 819 |
Author: 宋子奇 |
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Description: 一个verilog实现的crc校验,用于fpga实现,快速,准确有效
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Size: 1440278 |
Author: 枫叶鹏 |
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Description: 用Verilog编写crc校验码,包括8位,12位,16位,32位,非常实用
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Size: 11138 |
Author: asd |
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Description: 用于10M,100M,1000M以太网的并行CRC算法,有别于一般的CRC算法。verilog描述
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Size: 1469 |
Author: winwalk |
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Description: rfid中crc模块的verilog代码
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Size: 1056 |
Author: yan zeng |
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Description: verilog 实现循环冗余校验
源代码
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Size: 367681 |
Author: 长空 |
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Description: 这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.-PCM telephone transmission system Verilog model of procedures is a modlesim development environment under the project documents, and a waveform simulation results.
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Size: 47104 |
Author: way |
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Description: 用Verilog写的CRC校验程序 非常不错-Written using Verilog procedures are very good CRC Checksum
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Size: 486400 |
Author: westspeed |
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Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
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Size: 1024 |
Author: 张纪强 |
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Description: HDLC控制协议中CRC校验码算法代码,为CRC16,Verilog语言-HDLC Control Protocol Code in the CRC checksum algorithm code for CRC16, Verilog language
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Size: 1024 |
Author: 刘彻 |
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Description: 以太网的vhdl和verilog代码,供大家学习-Ethernet VHDL and Verilog code for everyone to learn
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Size: 934912 |
Author: sunlee |
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Description: CRC编码verilog代码,用于实现crc编码功能-CRC coding Verilog code for CRC encoding capabilities to achieve
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Size: 1024 |
Author: 龙一 |
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Description: FPGA大量实例,仅供参考,适合新手学习-FPGA a large number of examples for reference only, suitable for novices to learn
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Size: 2601984 |
Author: Sem |
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Description: 用verilog语言实现的的的32位CRC生成与检验的代码-The 32bits CRC using hardware describe language of verilog
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Size: 1024 |
Author: 朱猪 |
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Description: 用 UART 做文件传输(采用 Xmodem协议).pdf-Xmodem Protol
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Size: 506880 |
Author: 王晓斌 |
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Description: UVM简单例程,DUT为Verilog小程序。(UVM simple routine, DUT is Verilog applet.)
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Size: 5120 |
Author: wenxulyu
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Description: 包括下面文档:
readme.txt : This file
crc8_8.v : CRC-8, 8-bit data input.
crc12_4.v : CRC-12, 4-bit data input.
crc16_8.v : CRC-16, 8-bit data input.
crc_ccit_8.v : CRC-CCIT, 8-bit data input.
crc32_8.v : CRC-32, 8-bit data input.
crcgen.pl : Perl script used to generate Verilog Source for CRC
caluculation.(Contains the following files
readme.txt : This file
crc8_8.v : CRC-8, 8-bit data input.
crc12_4.v : CRC-12, 4-bit data input.
crc16_8.v : CRC-16, 8-bit data input.
crc_ccit_8.v : CRC-CCIT, 8-bit data input.
crc32_8.v : CRC-32, 8-bit data input.
crcgen.pl : Perl script used to generate Verilog Source for CRC
caluculation.)
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Size: 10240 |
Author: chris_lj
|
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Description: design crc module in data network transmission
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Size: 2048 |
Author: Zick |
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Description: Verilog的135个经典设计实例,部分摘录如下:【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】(7,4)循环码纠错译码器【例 12.10】(7,4)线性分组码译码器【例 12.7】11 阶FIR 数字滤波器。。。。。。。(135 classic examples of Verilog design)
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Size: 167936 |
Author: 三棵树机务段 |
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